The field of the invention is integrated circuit processing, in particular low-capacitance high speed circuits.
It is well known in the field that junction capacitance between sources and drains (S/D) and the substrate is an important limiting factor in circuit performance. In addition, S/D to substrate leakage results in useless power consumption. Furthermore, contacts to SID diffusions may suffer form reliability concerns if the etch of the contacts places the conductive material of the contact in close proximity to the bottom junction edge through overetch or misalignment.
Silicon on insulator technology has less junction capacitance than bulk technology because the buried insulator reduces the capacitance, but is more expensive.
It is desirable to develop a low-capacitance transistor structure with low SID leakage for bulk silicon integrated circuits that is economical to manufacture.
A feature of the invention is the formation of conductive contact pads over a portion of the STI to reduce the area, reduce capacitance and leakage between the source/drain and the silicon substrate.
Another feature of the invention is a reduced size of the transistor area within the shallow trench isolation (STI) that is less than would have been required to provide space for contacts to the rest of the circuit if these contacts were fully within the active region.